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I learnt recently that Sandy Bridge uses a micro-instruction cache akin to the execution trace cache in Netburst. From what I know, many of the simpler x86 instructions (those translating into 4 micro-instructions or less) are decoded by hardwired decoders without any help from the microcode ROM, which is fairly a fast and simple process involving no table lookup. So, why would one cache the decoded micro-instructions and then look for them later, when they can be more easily translated by the decoder circuitry.

Is the cache only used for more complex instructions involving microcode ROM lookup? Or is there some higher wisdom involved.

Kraken
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    Intel has generally limited instruction fetch to 16 byte blocks, the micro-op cache can provide up to 4 ops per cycle from a 32B chunk. For x86, storage of decoded instructions is more energy efficient than denser non-decoded instruction cache with dynamic decoding. The decoded cache can also be considered an L0 cache (lower latency with decent hit rate). There is also potential for decode-time optimizations. See http://www.realworldtech.com/haswell-cpu/2/ –  Aug 18 '16 at 01:05
  • So, its about the storage... – Kraken Aug 18 '16 at 07:18

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