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What books and articles can you recommend to learn basis of cache coherence problems in big SMP systems (which are NUMA and ccNUMA really) with >=16 cpu sockets?

Something like SGI Altix architecture analysis may be interesting.

What protocols (MOESI, smth else) can scale up well?

osgx
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If you would like to learn in detail then, "Parallel Computer Architecture: A Hardware/Software Approach" book is authoritative guide to this subject.

Also you would find slides at this site quite useful. (Lec 8-10)

Chintan Parikh
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  • Parallel Computer Architecture: A Hardware/Software Approach ~ David Culler (Author), J.P. Singh (Author), Anoop Gupta (Author) 1999 -ed2 – osgx Mar 15 '10 at 10:19
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I would have a look through docs.sun.com for documentation for the UltraSPARC CPU as well as some of their bigger systems. They've been dealing with issues like this for a long, long time, and their documentation is usually excellent.

Here's a good place to start: http://www.google.com/search?q=cache+coherence+site:docs.sun.com

Full disclosure: I used to hold a Sun badge.

Alex
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  • Can you provide more accurate links? Is there some survey of big systems memory issues? – osgx Mar 15 '10 at 10:26
  • @osgx: More accurate links will depend on exactly what sort of questions you have. Your best bet is to spend some time looking through their documentation and finding exactly which aspect interests you most, then drilling down further into that specifically. – Alex Mar 16 '10 at 00:04
  • "I used to hold a Sun badge" - what does this mean? – osgx Mar 16 '10 at 01:27
  • @osgx: Much like this one: http://lh5.ggpht.com/miles.min.xu/RqdpY8j-0qI/AAAAAAAAAcU/vYclVMeBHP0/DSCF0811.jpg – Alex Mar 16 '10 at 02:21