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While reading about PCIe and PCI I came across webpages detailing about the difference between Serial and Parallel communication. What I found out was one particular statement i.e.

Some things like PCI Express do the best of both worlds, they do a parallel set of serial connections (the 16x port on your motherboard has 16 serial connections). By doing that each line does not need to be in perfect sync with the other lines, just as long as the controller at the other end can reorder the "packets" of data as they come in using the correct order. Source

What i think is reordering will come into picture even in parallel communication also. So how will 16 parallel set of serial connections avoid the problem of synchronizing the data?

Thanks.

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nerd
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2 Answers2

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Parallel communication is subject to clock skew, while serial communication is not. A packet-based communication protocol allows multiple serial channels to operate in parallel without being adversely affected by clock skew.

  • Parallel communication is difficult to implement at very high speeds because the transmission of each bit can fall out of sync very fast. Not every signal travels at the same speed, and the speed of the entire communication channel is limited by the slowest signal. This is called clock skew.

  • Reordering data in a parallel communication channel is not possible because one set of signals must be received in its entirety before the next set can be received. The signals do not contain the metadata needed to determine the order of the bits when the lines fall out of sync.

  • Serial communication avoids this issue because there is no such clock skew to deal with. Using multiple serial channels in parallel can significantly improve performance, although doing so introduces clock skew as the channels can drift out of sync with each other. However, this can be addressed in a manner not possible with a parallel bus.

  • Several high-speed serial buses, including PCI Express and USB, packetize the data stream, so that each channel can transfer data on its own, with the data reordered by the controller as needed. Each packet contains a header containing metadata as well as the actual data being transferred. This means that the correct data can be reconstructed even if the channels fall out of sync due to clock skew. PCI Express uses this technique to enable extremely high-speed communication with up to 32 lanes in parallel (though no more than 16 in practice).

bwDraco
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Reordering doesn't tend to be an issue of parallel communication because only one parallel bus is in use and data is sent in order.

What the text you quote means is each end point does not need to be in sync, thus it is possible that data will be received out of order as a whole, and so the mechanism in play should be able to detect and correct this.

Having a number of serial connections working in parallel does not solve the problem, it is the problem.

albal
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  • You missed the point here. You can't really reorder data in parallel communication. Each set of signals has to be received before the next set can be received. There's a problem called [clock skew](https://en.wikipedia.org/wiki/Clock_skew) involved here. – bwDraco Aug 11 '15 at 11:32